Programmable logic devices (PLD) are logic devices which can be programmed by a user to perform a specific logic function. They generally consist of a plurality of logic function generators which are connected one to another by an interconnection network. Programmable logic devices are known in which both the function generators and the interconnection network can be programmed. The logic function generator is commonly referred to as a unit cell, the programmable logic device (PLD) being a regular array of said unit cells. A number of such unit cells are known, those in common usage being discussed below. Field Programmable Gate Array (FPGA) is a generic term commonly used in the art for large capacity PLDs.
1) Fixed Gates
The unit cell is a logic gate having a fixed logic function, often a NAND gate in a CMOS device. It is known to construct an array of such gates with a programmable interconnection network, although the logic function of each unit is fixed. The programmability of the interconnection network arises by the provision of a multiplexer on the inputs of each NAND gate so that the inputs to each NAND gate can come from any of a number of different unit cells within the interconnection network. The array can then be programmed by setting a state of all of the multiplexers in the array, so that signals are correctly routed through the array.
2) Programmable Logic Arrays (PLA)
These arrays comprise a plurality of rows of switches, each row providing an output which is a logical OR of some of a plurality of inputs to the switches in that row. Each row is arranged to receive a set of inputs and their inverses. The logic function to be implemented by the array is set by setting the state of the switches. The same structure can also be used to generate a logical AND function. It is known to use a programmable logic array to provide outputs which are used as the inputs to a second such array, and these are often referred to as AND plane/OR plane structures.
3) Look-Up Tables (LUT)
The basic unit cell for a look-up table is a small random access memory comprising a plurality of memory cells. Inputs to the memory provide the address for the memory, and the output is the data read from the cell at the addressed memory location. By storing appropriate data in the memory, it is possible to generate any Boolean function of a number of variables up to the address width of the memory.
The fixed gate array, the PLA switch and the LUT cell are all programmed by storing data according to the logic function to be implemented. In the PLA, this data controls the state of the switches of the PLA; in the LUT, this data is stored in the memory cell; and in the fixed gate array the data controls the routing connections of the multiplexers.
The various types of programmable logic devices set out above have different characteristics so that they are preferred for certain logic manipulations and less preferred for others. The following table gives a general guide as to the good points and bad points of each type of programmable logic device.
______________________________________ Cell type Good at: Bad at: ______________________________________ Fixed Logic which uses the Logic using other Gate same gate as the gates basic cell PAL/PLA 1) multiple input Complex functions of AND and OR gates few inputs (e.g. (such as decoders) exclusive OR) Hence 2) AND-plane/OR- Adders, parity plane (sum of generators etc. are products) designs hard Lookup Table Can implement any Gates with many more function of its inputs than the unit inputs. Hence cell (big comparators, adders, simple decoders etc.) parity etc. are easy. ______________________________________
Thus, a user who has selected a particular programmable logic device based on his preferred implementation will find that he does not have the versatility to use that logic device to optimum effect in different logic applications. The present invention seeks to provide a programmable logic device which is more versatile.